Etepic

' AD9833 Master Clock 1.4 MHz


DEFINE OSC 4
DEFINE OSCCAL_1K 1
#CONFIG
#LIST_12F675
 __CONFIG _INTRC_OSC_NOCLKOUT & _WDT_OFF & _PWRTE_ON & _MCLRE_OFF & _CP_OFF & _BODEN_OFF
#ENDCONFIG

TRISIO= %00000000 : GPIO= 0 : CMCON= 7 : ANSEL= 0 : ADCON0= 0 : VRCON.7= 0
OPTION_REG.7= 0 : WPU= %00000000
   
'SYMBOL DAT= GPIO.2              ; DDS Pin Serial Data     for DATA   Pin 7
'SYMBOL CLK= GPIO.4              ; DDS Pin W CLK           for CLOCK  Pin 6
'SYMBOL ENA= GPIO.5 : LOW ENA    ; DDS Pin FQ UD           for ENABLE Pin 5

 Pause 200                  ' Let Everything Power Up


DAT  VAR GPIO.2              ; Data Signal is   ON GPI0.0, Pin 
CLK  VAR GPIO.4              ; Clock Signal is  ON GPIO.1, Pin  
ENA  VAR GPIO.5 : LOW ENA    ; Frequency Update ON GPIO.2, Pin  

DEFINE SHIFT_PAUSEUS 2       ; DATA Speed

                            ' Register Start Sending  Train
                            ' CONTROL SET RESET, FREQ0 ACTIVE ,
                            ' Frequency LSB LOW  FREQUENCY WORD ,
                            ' Frequency MSB HIGH FREQUENCY WORD ,
                            ' PHASE REGISTER ,
                            ' PRESET CLEAR RESET .
                                                         
' 1 KHz Sine                             
    SHIFTOUT DAT, CLK, 1, [$21,$00,$60,$42,$43,$95,$C0,$00,$20,$00]

' Last Line $20,$00 Sine , $20,$02 Triangle , $20,$28 Square

    ENA= 1 : PauseUS 10 : ENA= 0   ' Now pulse the Frequency Update Pin
  
Start: ; *#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*

      GOTO Start

' AD9833 Master Clock 1.4 MHz

DEFINE OSC 4
DEFINE OSCCAL_1K 1
#CONFIG
#LIST_12F675
 __CONFIG _INTRC_OSC_NOCLKOUT & _WDT_OFF & _PWRTE_ON & _MCLRE_OFF & _CP_OFF & _BODEN_OFF
#ENDCONFIG

TRISIO= %00000000 : GPIO= 0 : CMCON= 7 : ANSEL= 0 : ADCON0= 0 : VRCON.7= 0
OPTION_REG.7= 0 : WPU= %00000000
   
'SYMBOL DAT= GPIO.2              ; DDS Pin Serial Data     for DATA   Pin 7
'SYMBOL CLK= GPIO.4              ; DDS Pin W CLK           for CLOCK  Pin 6
'SYMBOL ENA= GPIO.5 : LOW ENA    ; DDS Pin FQ UD           for ENABLE Pin 5

 Pause 1000                  ' Let Everything Power Up


DAT  VAR GPIO.2              ; Data Signal is   ON GPI0.0, Pin 
CLK  VAR GPIO.4              ; Clock Signal is  ON GPIO.1, Pin  
ENA  VAR GPIO.5 : LOW ENA    ; Frequency Update ON GPIO.2, Pin  

DEFINE SHIFT_PAUSEUS 50      ; DATA Speed

                            ' Register Start Sending  Train
                            ' CONTROL SET RESET, FREQ0 ACTIVE ,
                            ' Frequency LSB LOW  FREQUENCY WORD ,
                            ' Frequency MSB HIGH FREQUENCY WORD ,
                            ' PHASE REGISTER ,
                            ' PRESET CLEAR RESET .
                                                      
' 1.4 MHz Sine                             
'    SHIFTOUT DAT, CLK, 1, [$2100\16]
'    SHIFTOUT DAT, CLK, 1, [$6042\16]
'    SHIFTOUT DAT, CLK, 1, [$4395\16]
'    SHIFTOUT DAT, CLK, 1, [$C000\16]
'    SHIFTOUT DAT, CLK, 1, [$2000\16]

 SHIFTOUT DAT, CLK, 1, [$2100\16,$6042\16,$4395\16,$C000\16,$2000\16]
' Last Line $20,$00 Sine , $20,$02 Triangle , $20,$28 Square

    ENA= 1 : PauseUS 10 : ENA= 0   ' Now pulse the Frequency Update Pin
  
Start: ; *#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*

      GOTO Start

/*
 *  1.4 MHz SSB Exciter Modulator
 */

// PIC12F675 Configuration Bit Settings

// CONFIG1
#pragma config FOSC = INTRCIO   // Oscillator Selection bits (INTOSC oscillator: I/O function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN)
#pragma config WDTE = OFF       // Watchdog Timer Enable bit (WDT disabled)
#pragma config PWRTE = ON       // Power-Up Timer Enable bit (PWRT disabled)
#pragma config MCLRE = OFF      // MCLR master clear reset bit disabled
#pragma config BOREN = OFF      // Brown-out Detect Enable bit (BOD disabled)
#pragma config CP = OFF         // Code Protection bit (Program Memory code protection is disabled)
#pragma config CPD = OFF        // Data Code Protection bit (Data memory code protection is disabled)
#include <xc.h>
#include <pic12f675.h>

typedef unsigned char		BYTE;
typedef unsigned short int	WORD;
typedef unsigned long int	DWORD;
typedef enum _BOOL { FALSE = 0, TRUE }	BOOL;

typedef union {
    struct {
		BYTE			:8;
		BYTE			:4;
		BYTE D12		:1;
		BYTE D13		:1;
		BYTE D14		:1;
		BYTE D15		:1;
	};
    struct {
		BYTE 			:1;
		BYTE MODE		:1;
		BYTE 			:1;
		BYTE DIV2		:1;
		BYTE 			:1;
		BYTE OPBITEN	:1;
		BYTE SLEEP12	:1;
		BYTE SLEEP1		:1;
		BYTE RESET		:1;
		BYTE 			:1;
		BYTE PSEL		:1;
		BYTE FSEL		:1;
		BYTE HLB		:1;
		BYTE B28		:1;
		BYTE			:1;
		BYTE			:1;
	};
	WORD wValue;
} AD9833reg_t;

#define AD9833_SYNC		GPIO5
#define AD9833_SCLK		GPIO4
#define AD9833_SDAT		GPIO2

//=================================================================

static void AD9833_Reset(void);
static void AD9833_SetFreq(DWORD dwVal);
static void AD9833_SetPhase(WORD wVal);
static void AD9833_Start(BOOL bSquare);
static void AD9833_Send(WORD wData);

// FOSC There is no need to wait because the
#define DelayUs(x)
#define DelayNs(x)

static AD9833reg_t AD9833;

//=================================================================

// Main
void main(void)
{
	// Port Initialization
	GPIO = 0;
	
	AD9833_SYNC = 1;
	AD9833_SCLK = 1;
	AD9833_SDAT = 0;
    
    ADCON0 = 0x00;       // Internal ADC OFF
    ANSEL  = 0x00;       // All Analog selections pins are assigned as digital I/O
    CMCON  = 0x07;		 // Shut off the Comparator
    VRCON  = 0x00;       // Shut off the Voltage Reference
    TRISIO = 0x08;       // set as output except GP3
    GPIO   = 0x00;       // set all pins Low  

	
	AD9833_Reset();

	// Frequency Settings
	  AD9833_SetFreq(0x0E56042); // 1.4 MHz Calculation Eddystone Orion 5500 ###### Entry Frequency Here ######
	//AD9833_SetFreq(0x51EB852); // 8 MHz
	//AD9833_SetFreq(0x28F5C29); // 4 MHz
	//AD9833_SetFreq(0x147AE14); // 2 MHz
	//AD9833_SetFreq(0x0A3D70A); // 1 MHz    
	//AD9833_SetFreq(0x04A8C15); // 455 KHz
	
	// Start output
	AD9833_Start(FALSE);
	
	for(;;);

	return;
}

//  AD9833 Initialization
static void AD9833_Reset(void)
{
	AD9833.wValue = 0;

	AD9833.B28 = 1;     // Always write 28bit
	AD9833.RESET = 1;
	AD9833.SLEEP1 = 1;  // Internal clock disabled
	AD9833.SLEEP12 = 1; // DAC powered down
	
	AD9833_Send(AD9833.wValue);
}

// AD9833 Frequency Settings
static void AD9833_SetFreq(DWORD dwVal)
{
	AD9833reg_t Reg1, Reg2;

	Reg1.wValue = dwVal & 0x3FFF;
	Reg2.wValue = dwVal >> 14;
	
	// FREQ0/1 Use alternately
	if (AD9833.FSEL == 0)
	{
		// FREQ1 Write to
		AD9833.FSEL = 1;
		Reg1.D15 = 1;
		Reg2.D15 = 1;
	}
	else
	{
		// FREQ0 Write to
		AD9833.FSEL = 0;
		Reg1.D14 = 1;
		Reg2.D14 = 1;
	}

	AD9833_Send(Reg1.wValue);
	AD9833_Send(Reg2.wValue);

	// FREQ0/1 switching
	AD9833_Send(AD9833.wValue);
}

// AD9833 Phase Setting
static void AD9833_SetPhase(WORD wVal)
{
	AD9833reg_t Reg;
	Reg.wValue = wVal;

	// Always PHASE0 Write to
	Reg.D15 = 1;
	Reg.D14 = 1;
	Reg.D13 = 0;

	AD9833_Send(Reg.wValue);
}

// AD9833 Action Start
static void AD9833_Start(BOOL bSquare)
{
	AD9833.RESET = 0;
	AD9833.SLEEP1 = 0;
	AD9833.SLEEP12 = 0;
	
	if (bSquare)
	{
		AD9833.SLEEP12 = 1;
		AD9833.OPBITEN = 1;
		AD9833.DIV2 = 1;
	}
	
	AD9833_Send(AD9833.wValue);
}

// AD9833 Send to
static void AD9833_Send(WORD wData)
{
	AD9833_SYNC = 0;

	int nCount = 0;
	do
	{
		AD9833_SDAT = (wData & 0x8000)? 1 : 0;
		DelayNs(5); // t7, t9
		
		AD9833_SCLK = 0;
		DelayNs(10);      // t6
		AD9833_SCLK = 1;
		DelayNs(5);      // t5-t9
		
		wData <<= 1;
	}
	while (++nCount < 16);
	
	AD9833_SYNC = 1;
	DelayNs(5);          // t11
}

SHIFTOUT DAT, CLK, 5, [$21,$00,$60,$42,$40,$e5,$C0,$00,$20,$00]

ENA= 0 : PauseUS 1 : ENA= 1